1. Field of the Invention
The present invention relates in general to the field of semiconductor silicon device verification, and more particularly to a system and method for isolation of test environment errors from silicon errors detected during semiconductor device verification.
2. Description of the Related Art
Semiconductor devices, such as processors, are typically subjected to extensive testing and verification to debug silicon errors before commercial production begins. For instance, semiconductor processor devices are generally designed to perform logical operations on input data in order to provide expected output data. Once a design of inputs and expected outputs is complete, the design is laid out as a circuit pattern design that accepts the inputs to provide the expected outputs. Computer simulations of the circuit design are typically used to aid in verification that the circuit design will respond to inputs with the expected outputs. Processor debug begins once physical silicon devices are fabricated after the initial design is completed. Debug generally involves two major components, functional verification to verify that the processor device operates correctly at a nominal operating point, and electrical characterization to expand verification beyond the nominal operating point to make sure the device operates properly at specified electrical and environmental limits. Verification testing of a physical semiconductor device, typically done on high speed automated test equipment (ATE), allows identification and correction of semiconductor device faults.
Verification of a physical semiconductor device generally involves sending a stimulus into the device and measuring the response to the stimulus output by the device. If a predetermined stimulus results in an expected response, the physical semiconductor device has processed the input as designed. If a predetermined stimulus results in a response other than the expected response, the semiconductor device is considered to have failed to process the input as designed. For instance, functional verification initializes the processor to a known state, executes code sequences on the processor and compares the results of the instructions with simulated values or values obtained from a previous architectural reference. Functional verification uses focused cases to test areas of functionality that are risky or difficult to test and pseudo-randomly generated instructions and data for finding other functional bugs. The pseudo-random instructions are simulated in an architectural simulator and then applied to the processor under test to ensure that the architectural state from the simulator and the processor match. If a failure to match occurs in which the processor fails to process a stimulus as simulated, the diagnostic failure is typically debugged to isolate and correct the cause of the failure by analyzing the failing signatures. Electrical characterization verification often applies similar stimuli but with variations in environmental conditions and with process variation. After completion of physical verification, the semiconductor device is generally fabricated in batches and sold commercially. Complete and accurate verification of the semiconductor device reduces the occurrence of post-release bugs that are both embarrassing and costly to fix.
The test environment for silicon bring up and debug is not dependent on system limitations, but rather allows variations in voltage, frequency and temperature as well as freedom to adjust timing and voltage swings on a per-pin basis. Silicon device inputs and outputs are determined by a pattern that is generated by a simulator or even by hand to give an extremely flexible environment to characterize the silicon device and debug performance issues. One difficulty with physical silicon verification of a semiconductor device occurs when errors are caused by the verification environment rather than the semiconductor device itself. For instance, verification errors occur if the tester or system that applies stimulus to the semiconductor device either applies an incorrect stimulus or mismatches a stimulus and its expected response. An improper stimulus might be applied due to hardware or software failures in the verification environment, such as poor calibration of signals or faulty circuits that provide the stimulus to the semiconductor device. A mismatch between a predetermined stimulus and its expected response might occur if the translation of expected responses to predetermined stimulus is performed incorrectly from the computer simulation file format to the tester file format. When a diagnostic failure occurs during physical testing of a semiconductor device, test engineers generally debug the error to detect whether the error was introduced by the verification environment or the semiconductor device. Debugging of both the device and the verification environment increases the complexity and duration of the verification process.